1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a Delay-Locked Loop (DLL) circuit for a semiconductor device and a method of driving the same.
2. Description of the Related Art
In general, a DLL circuit is used to provide a delay locked clock having a phase, which is earlier than the phase of an internal clock by a specific time, obtained by converting an external clock. An internal clock used in a semiconductor integrated circuit is delayed through a clock buffer and transmission lines, and thus, a phase difference occurs between the internal clock and an external clock. A DLL circuit may be used to solve concerns in which the output timing of output data is not synchronized due to the phase difference.
FIG. 1 is a waveform diagram illustrating the operation of a conventional DLL circuit.
As shown in FIG. 1, the DLL circuit outputs a delay locked clock signal DLL_OUT having a timing that is earlier than a timing of a received internal clock INT_CLK by a specific time. A semiconductor memory device synchronizes data D0, D1, and D2 with the delay locked clock signal DLL_OUT and outputs the synchronized data. When the semiconductor memory device outputs the data as described above, the data seems to be precisely outputted in response to an external signal EXT_CLK.
When the DLL circuit completes the delay locked operation, a locking detector detects this completion and activates a locking detection signal. When the locking detector activates the locking detection signal, the semiconductor memory device externally outputs data synchronized with a transition of a delay locked clock that is outputted from the DLL circuit.
If the locking detector determines that a delay locked operation has been completed even when the delay locked operation has not been completed, and thus, activates a locking detection signal, the semiconductor memory device erroneously detects that the delay locked operation has been completed and outputs data externally. In this case, the output data may not be synchronized with an external system clock.
Furthermore, a delay locked operation may not be completed because a locking detection signal is not activated when the delay locked operation is completed. Even in this case, the output data may not be synchronized with an external system dock. As a result, an external device may not properly receive data outputted from a semiconductor memory device,